Fast Multiplication Without Carry-Propagate Addition
IEEE Transactions on Computers
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Carry-Save Multiplication Schemes Without Final Addition
IEEE Transactions on Computers
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Practical low power digital VLSI design
Practical low power digital VLSI design
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
High performance low power array multiplier using temporal tiling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Power compiler: a gate-level power optimization and synthesis system
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Analysis of Column Compression Multipliers
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
High-level optimization techniques for low-power multiplier design
High-level optimization techniques for low-power multiplier design
Computational Aspects of VLSI
A low-power multiplier with the spurious power suppression technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-speed radix-4 multiplexer-based array multiplier
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Modified booth multipliers with a regular partial product array
IEEE Transactions on Circuits and Systems II: Express Briefs
A spurious-power suppression technique for multimedia/DSP applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Journal of Signal Processing Systems
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We present a high-performance low-power design of linear array multipliers based on a combination of the following techniques: signal flow optimization in [3:2] adder array for partial product reduction, left-to-right leapfrog (LRLF) signal flow, and splitting of the reduction array into upper/lower parts. The resulting upper/lower LRLF (ULLRLF) multiplier is compared with tree multipliers. From automatic layout experiments, we find that ULLRLF multipliers have similar power, delay, and area as tree multipliers for n \leq 32. With more regularity and inherently shorter interconnects, the ULLRLF structure presents a competitive alternative to tree structures in the design of fast low-power multipliers implemented in deep submicron VLSI technology.