Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
Reducing power with dynamic critical path information
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Picking Statistically Valid and Early Simulation Points
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper presents a hardware technique to reduce of static and dynamic power consumption in FUs. This approach entails substituting some of the power-hungry adders of a 64-bit superscalar processor, by others with lower power-consumption, and modifying the slot protocol in order to issue as much instructions as possible to those low power consumption units incurring marginal performance penalties. Our proposal saves between a 2% and a 45% of power-performance in FUs and between a 16% and a 65% of power-consumption in adders.