Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Energy-efficient signal processing using FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Performance benefits of monolithically stacked 3D-FPGA
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Power-aware RAM mapping for FPGA embedded memory blocks
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Energy- and time-efficient matrix multiplication on FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-aware FPGA logic synthesis using binary decision diagrams
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Low-complexity high-speed decoder design for quasi-cyclic LDPC codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
ACM Transactions on Embedded Computing Systems (TECS)
Novel Low Power, High Speed Hardware Implementation of 1D DCT/IDCT Using Xilinx FPGA
ICCTD '09 Proceedings of the 2009 International Conference on Computer Technology and Development - Volume 01
Energy reduction with run-time partial reconfiguration (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes
Allerton'09 Proceedings of the 47th annual Allerton conference on Communication, control, and computing
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
Proceedings of the Conference on Design, Automation and Test in Europe
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint (3,k)-regular LDPC code and decoder/encoder design
IEEE Transactions on Signal Processing
Active leakage power optimization for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Device and Architecture Cooptimization for FPGA Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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We explore the use of Data-Level Parallelism (DLP) as a way of improving the energy efficiency and power consumption involved in running applications on an FPGA. We show that static power consumption is a significant fraction of the overall power consumption in an FPGA and that it does not change significantly even as the area required by an architecture increases, because of the dominance of interconnect in an FPGA. We show that the degree of DLP can be used in conjunction with frequency scaling to reduce the overall power consumption.