Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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Device optimization considering supply voltage Vdd and threshold voltage Vt has little chip-area increase but a great impact on power and performance in the nanometer technology. This paper studies simultaneous evaluation of device and architecture optimization for field-programmable gate arrays (FPGAs). We first develop an efficient yet accurate timing and power evaluation method called a trace-based model. By collecting trace information from a cycle-accurate simulation of placed and routed FPGA benchmark circuits and reusing the trace for different Vdds and Vts, we enable device and architecture cooptimization considering hundreds of device and architecture combinations. Compared to the baseline FPGA architecture, which uses the Versatile Place and Route architecture model and the same lookup table and cluster sizes as those used by the Xilinx Virtex-II, Vdd suggested by the International Technology Roadmap for Semiconductor, Vt optimized with respect to the preceding architecture, and Vdd architecture and device cooptimization can reduce the energy-delay product (ED) by 20.5% and the chip area by 23.3%. Furthermore, considering the power gating of unused logic blocks and interconnect switches (in this case, sleep transistor size is a parameter of device tuning), our co-optimization reduces ED by 55.0% and the chip area by 8.2% compared to the baseline FPGA architecture. To the best of our knowledge, this is the first in-depth study in the literature on architecture and device cooptimization for FPGAs.