Modeling and estimating leakage current in series-parallel CMOS networks
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Measurement of voltage flicker and implementation using FPGA
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Thermal-aware reliability analysis for platform FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WSEAS Transactions on Circuits and Systems
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Analysis of extensive power factor by FPGA under power quality disturbance
IMCAS'10 Proceedings of the 9th WSEAS international conference on Instrumentation, measurement, circuits and systems
Design of accurate power factor measurement approach using FPGA-based chip
WSEAS Transactions on Circuits and Systems
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Subthreshold leakage modeling and estimation of general CMOS complex gates
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Off-path leakage power aware routing for SRAM-based FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
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Active leakage power dissipation is considered in field-programmable gate arrays (FPGAs) and two "no cost" approaches for active leakage reduction are presented. It is well known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. The authors' first leakage reduction technique leverages a fundamental property of basic FPGA logic elements [look-up tables (LUTs)] that allows a logic signal in an FPGA design to be interchanged with its complemented form without any area or delay penalty. This property is applied to select polarities for logic signals so that FPGA hardware structures spend the majority of time in low-leakage states. In an experimental study, active leakage power is optimized in circuits mapped into a state-of-the-art 90-nm commercial FPGA. Results show that the proposed approach reduces active leakage by 25%, on average. The authors' second approach to leakage optimization consists of altering the routing step of the FPGA computer-aided design (CAD) flow to encourage more frequent use of routing resources that have low leakage power consumptions. Such "leakage-aware routing" allows active leakage to be further reduced, without compromising design performance. Combined, the two approaches offer a total active leakage power reduction of 30%, on average.