Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Proceedings of the 6th international workshop on Hardware/software codesign
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Simulation of Task Graph Systems in Heterogeneous Computing Environments
HCW '99 Proceedings of the Eighth Heterogeneous Computing Workshop
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Combining low-leakage techniques for FPGA routing design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Proceedings of the 42nd annual Design Automation Conference
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Active leakage power optimization for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.01 |
As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabrics. In particular, we focus on eliminating leakage waste due to the delay between reconfiguration and execution time of a task. For partially dynamically reconfigurable FPGAs, the configuration prefetching technique is commonly used to hide runtime reconfiguration overhead. With prefetching, the configuration of a task is loaded into FPGAs as early as possible. Therefore, there is often a delay between reconfiguration and execution time of a task. In this period of time, the SRAM cells allocated to a task cannot be turned off even though they are not utilized. In this article, we propose a two-stage task scheduling methodology to reduce leakage waste due to the delay between reconfiguration and execution time of a task without sacrificing performance. In the first stage, a performance-driven task scheduler that targets at minimizing the schedule length is invoked to generate an initial placement. In the second stage, a postplacement leakage-aware task scheduling is applied to refine the initial placement such that leakage waste is minimized provided that the schedule length is not increased. To solve the postplacement leakage optimization problem, we propose two algorithms. The first one is an optimal algorithm based on Integer Linear Programming (ILP). The second algorithm is a heuristic approach that iteratively refines the placement to reduce leakage waste. Experimental results on real and synthetic designs show that the efficiency and effectiveness of the proposed postplacement leakage reduction techniques.