Introduction to algorithms
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
Placement of digital microfluidic biochips using the t-tree formulation
Proceedings of the 43rd annual Design Automation Conference
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
3-D floorplanning using labeled tree and dual sequences
Proceedings of the 2008 international symposium on Physical design
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The O-Sequence: Representation of 3D-Dissection
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
IEICE - Transactions on Information and Systems
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Droplet-routing-aware module placement for cross-referencing biochips
Proceedings of the 19th international symposium on Physical design
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Architecture-Aware reconfiguration-centric floorplanning for partial reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
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Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topological floorplan representation, named 3D-subTCG (3-Dimensional sub-Transitive Closure Graph) to deal with the 3-dimensional (temporal) floorplanning/placement problem, arising from dynamically reconfigurable FPGAs. The 3D-subTCG uses three transitive closure graphs to model the temporal and spatial relations between modules. We derive the feasibility conditions for the precedence constraints induced by the execution of the dynamically reconfigurable FPGAs. Because the geometric relationship is transparent to 3D-subTCG and its induced operations, we can easily detect any violation of temporal precedence constraints on 3D-subTCG. We also derive important properties of the 3D-subTCG to reduce the solution space and shorten the running time for 3D (temporal) foorplanning/placement. Experimental results show that our 3D-subTCG based algorithm is very effective and efficient.