Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Understanding metrics in logic synthesis for routability enhancement
Proceedings of the 2003 international workshop on System-level interconnect prediction
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 international workshop on System level interconnect prediction
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Physical Design for 3D System on Package
IEEE Design & Test
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
3-D floorplanning using labeled tree and dual sequences
Proceedings of the 2008 international symposium on Physical design
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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New technologies such as 3D integration are becoming a new force that is keeping Moore's law in effect in today's nano era. By adding a third dimension in current 2D circuits, we can greatly increase integration density, reduce interconnection length, and enable heterogeneous systems within one package. In order to exploit the advantages of 3D integration, layout designers and tool developers need to be fully aware of this rapid development. This paper gives an overview of recent 3D integration technologies, such as 3D packages and 3D integrated circuits. We then analyze and compare 3D data structures in order to draw conclusions about their future potential. Finally, the impact of 3D technologies on interconnect prediction is discussed.