Performance analysis and technology of 3-D ICs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Layout effects in fine grain 3D integrated regular microprocessor blocks
Proceedings of the 48th Design Automation Conference
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This work examines the impact of interstratal interconnect density on the wire-length distribution and on the performance of three-dimensional integrated circuits. A model for the wire-length distribution of 3D-ICs, which takes into account the interstratal interconnect density, is proposed first. The wire-length distributions of 2D-IC, homogeneous (ideal), semi-ideal and realistic 3D-ICs containing two strata are generated using the established model. Finally, the system-level performance of these circuits is assessed by evaluating the delay time and the dynamic switching energy of a critical path containing several interconnected inverters. The lengths of wires connecting inverters are randomly sampled from the wire-length distributions of the circuits under investigation. The inverters and interconnects have electrical properties of recent proposals for the 45-nm technology node.