Computational geometry: an introduction
Computational geometry: an introduction
Approximation algorithms for bin packing: a survey
Approximation algorithms for NP-hard problems
Synthesis and floorplanning for large hierarchical FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Circuit partitioning for dynamically reconfigurable FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Bottomn-Left Bin-Packing Heuristic: An Efficient Implementation
IEEE Transactions on Computers
Proceedings of the 38th annual Design Automation Conference
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
A C to Hardware/Software Compiler
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are still many challenging problems to be solved before any practical general-purpose reconfigurable system is built. One fundamental issue is the placement of the modules on the reconfigurable functional unit (RFU).In this paper we present an online heuristic placement method with overall O(n log n) space complexity and O(log n) time complexity for each insertion/deletion of modules on the RFU chip, 'n' being the number of modules currently on the RFU. Our proposed method is O(n) faster than an algorithm which considers all possible locations for placing a new module, but as experimental results show its quality is 7% worse.