Data-parallel C on a reconfigurable logic array
The Journal of Supercomputing - Special issue on field programmable gate arrays
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FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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AUIC '05 Proceedings of the Sixth Australasian conference on User interface - Volume 40
Performance improvements from partitioning applications to FPGA hardware in embedded SoCs
The Journal of Supercomputing
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A partitioning flow for accelerating applications in processor-FPGA systems
ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Performance gains from partitioning embedded applications in Processor-FPGA socs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Improvements in the FPGA technology have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. This paper presents a top-down compilation method, under development, for such systems. We compile a C program into hierarchical VHDL source files, and annotate them with the placement information of the hardware modules to be configured on the FPGA. Static scheduling combined with a fast, two-stage placement core reduces the compilation time of large programs to minutes.