A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The Garp Architecture and C Compiler
Computer
A C to Hardware/Software Compiler
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a hardware/software partitioning method for improving performance in single-chip embedded systems comprised by processor and Field Programmable Gate Array reconfigurable logic. Speedups are achieved by executing critical software parts on the reconfigurable logic. A generic hybrid System-on-Chip platform, which can model existing processor-FPGA systems, is considered. The partitioning flow utilizes an automated analysis procedure at the basic-block level for detecting kernels in software. Three different instances of the considered generic platform and two sets of benchmarks are used in the experiments. For the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For an 8-bit platform, the speedups of eight DSP algorithms are considerably greater, since they range from 3.2 to 68.4.