Performance driven floorplanning for FPGA based designs

Authors:
Jianzhong Shi;Dinesh Bhatia
Affiliations:
Design Automation Laboratory, P.O. Box 210030, ECECS Department, University of Cincinnati, Cincinnati, OH;Design Automation Laboratory, P.O. Box 210030, ECECS Department, University of Cincinnati, Cincinnati, OH
Venue:
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Year:
1997

Citing 7
Cited 6

Optimal orientations of cells in slicing floorplan designs

Information and Control
Path-delay constrained floorplanning: a mathematical programming approach for initial placement

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An analytical approach to floorplan design and optimization

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing influenced force directed floorplanning

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A new algorithm for floorplan design

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Algorithms for VLSI Physical Design Automation

Algorithms for VLSI Physical Design Automation
Automatic floorplan design

DAC '82 Proceedings of the 19th Design Automation Conference

A methodology for fast FPGA floorplanning

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
On Using Tabu Search for Design Automation of VLSI Systems

Journal of Heuristics
Fast Template Placement for Reconfigurable Computing Systems

IEEE Design & Test
A New Floorplanning Method for FPGA Architectural Research

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fast Online Placement for Reconfigurable Computing

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Quantified Score

Hi-index	0.00

Visualization

Abstract

Increasing design densities on large FPGAs and greater demand for performance, has calledfor special purpose tools like floorplanner, performance driven router, and more. In this paper we present a floorplanning based design mapping solution that is capable of mapping macro cell based designs as well as hierarchicaldesigns on FPGAs. The mapping solution has been tested extensively on a large collection of designs. We not only outperform state of the art CAE tools from industry in terms of execution time but also achieve much better performance in terms of timing. These methods are especially suitable for mapping designs on very large FPGAs.