Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
The mathematics of nonlinear programming
The mathematics of nonlinear programming
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Performance-driven constructive placement
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic prediction of critical paths and nets for constructive timing-driven placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
| Hi-index | 0.00 |
A procedure for path-delay constrained initial placement during chip floorplanning is presented which directly incorporates timing and geometrical constraints into the process. The problem is modeled and mathematically formulated as a constrained non-linear programming problem which is systematically divided and solved in three steps: timing minimization with module overlap, module separation and timing minimization without module overlap. To save computation time, two techniques for eliminating non-logical and noncritical paths are used to reduce the number of paths considered during the optimization. Experimental results show that the placement results satisfy all given timing and geometrical constraints, and have good total normalized wire delays.