Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Path-delay constrained floorplanning: a mathematical programming approach for initial placement
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Iterative wirability and performance improvement for FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Effective Heuristics for Timing Driven Constructive Placement
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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A new approach to the performance-driven placement based on a window concept is presented. We first convert timing constraints to geometric shapes using the defined windows. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then a constructive placement process uses the window information to select an unplaced module, and to find an appropriate position for the module. This approach represents a unified way to consider both timing and geometric constraints during the placement process. The experimental results show that the improvement of circuit performance can be achieved by the sufficient use of the window information.