Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs

Authors:
Yasushi Ogawa;Tatsuki Ishii;Yoichi Shiraishi;Hidekazu Terai;Tokinori Kozawa;Kyoji Yuyama;Kyoji Chiba
Affiliations:
Central Research Laboratory, Hitachi Ltd, Higashi-koigakubo, Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi Ltd, Higashi-koigakubo, Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi Ltd, Higashi-koigakubo, Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi Ltd, Higashi-koigakubo, Kokubunji, Tokyo, 185, Japan;Central Research Laboratory, Hitachi Ltd, Higashi-koigakubo, Kokubunji, Tokyo, 185, Japan;Device Development Center, Hitachi Ltd;Kanagawa Works, Hitachi Ltd.
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

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Abstract

Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with “scope” and “zone”, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LST's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics.