Timing- and constraint-oriented placement for interconnected LSIs in mainframe design

  • Authors:
  • Yasushi Ogawa;Tsutomu Itoh;Yoshio Miki;Tatsuki Ishii;Yasuo Sato;Reiji Toyoshima

  • Affiliations:
  • Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan;Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan;Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan;Kanagawa Works, Hitachi, Ltd., Kanagawa, Japan;Device Development Center, Hitachi, Ltd., Tokyo, Japan;Hitachi Computer Engineering Company, Kanagawa, Japan

  • Venue:
  • DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
  • Year:
  • 1991

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Abstract