Automatic placement algorithms for high packing density V L S I

Authors:
T. Kozawa;H. Terai;T. Ishii;M. Hayase;C. Miura;Y. Ogawa;K. Kishida;N. Yamada;Y. Ohno
Affiliations:
Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Device Development Center, Hitachi Ltd.;Kanagawa Works, Hitachi Ltd.;Kanagawa Works, Hitachi Ltd.
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

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Abstract

Five placement procedures which combine three basic algorithms are developed and incorporated to our system. Evaluation of results is presented. Compared with manual design the optimum procedure reduces block size by 6.5%. The normalized area for one transistor (NA) is defined as the measure of automatic layout performance. NA is the product of wiring pitch. Optimum NA is confirmed to be 14.9 for manual design and 13.9 for automatic layout using the optimum procedure. This system is applicable to both custom logic LSIs and masterslice LSIs and has been applied to layouts of many such devices.