Automatic placement algorithms for high packing density V L S I
DAC '83 Proceedings of the 20th Design Automation Conference
Combine and top down block placement algorithm for hierarchical logic VLSI layout
DAC '84 Proceedings of the 21st Design Automation Conference
MILD - A cell-based layout system for MOS-LSI
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
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Routing algorithms for multi- (more than 3) sided pin arrangements are presented. These algorithms are essential for layouts mixing standard cells with custom macros such as ROM, RAM, PLA and ALU. An extended layout model in which these algorithms are applied is also presented. An experimental result regarding the effect on block area with respect to cell height, obtained by comparing an extended model with a traditional model, is described.