Combine and top down block placement algorithm for hierarchical logic VLSI layout

Authors:
Tokinori Kozawa;Chihei Miura;Hidekazu Terai
Affiliations:
Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN;Central Research Laboratory, Hitachi Ltd., Higashi Koigakubo, Kokubunji, Tokyo 185, JAPAN
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

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Abstract

A Combine and TOP down placement (CTOP) algorithm for determination of relative placement of blocks which are set of cells is presented. The objective functions of the CTOP algorithm are to minimize inter-block wiring space and dead space using a combine value P. P is defined as the combination of the connectivity and dead space factor. With use of the CTOP algorithm, chip size in our example is about 6% smaller than with manual block placement. In the experiment reported on here, we used the same automatic placement and routing program for intra-block design.