Evaluation of Placement Techniques for DNA Probe Array Layout

  • Authors:

  • Andrew B. Kahng;Ion Mandoiu;Sherief Reda;Xu Xu;Alex Z. Zelikovsky

  • Affiliations:

  • University of California at San Diego;University of Connecticut;University of California at San Diego;University of California at San Diego;Georgia State University

  • Venue:
  • Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2003

Quantified Score

Hi-index 0.00

Visualization

Abstract

DNA probe arrays have emerged as a core genomic technology thatenables cost-effective gene expression monitoring, mutation detection,single nucleotide polymorphism analysis and other genomicanalyses. DNA chips are manufactured through a highly scalableprocess, Very Large-Scale Immobilized Polymer Synthesis (VL-SIPS),that combines photolithographic technologies adapted fromthe semiconductor industry with combinatorial chemistry. Commerciallyavailable DNA chips contain more than a half millionprobes and are expected to exceed one hundred million probes inthe next generation. This paper is one of the first attempts to applyVLSI CAD methods to the problem of probe placement in DNAchips, where the main objective is to minimize total border cost(i.e., the number of nucleotide mismatches between adjacent sites).We make the following contributions. First, we propose severalpartitioning-based algorithms for DNA probe placement thatimprove solution quality by over 4% compared to best previouslyknown methods. Second, we give a simple in-place probe re-embeddingalgorithm with solution quality better than previous"chessboard" and batched greedy algorithms. Third, we experimentallyevaluate scalability and suboptimality of existing and newlyproposed probe placement algorithms. Interestingly, we find thatDNA placement algorithms appear to have better suboptimalityproperties than those recently reported for VLSI placement algorithms.