VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Equireplicate Balanced Binary Codes for Oligo Arrays
SIAM Journal on Discrete Mathematics
Fidelity Probes for DNA Arrays
Proceedings of the Seventh International Conference on Intelligent Systems for Molecular Biology
Enhanced Sequence Reconstruction with DNA Microarray Application
COCOON '01 Proceedings of the 7th Annual International Conference on Computing and Combinatorics
Selecting Optimum DNA Oligos for Microarrays
BIBE '00 Proceedings of the 1st IEEE International Symposium on Bioinformatics and Biomedical Engineering
Engineering a scalable placement heuristic for DNA probe arrays
RECOMB '03 Proceedings of the seventh annual international conference on Research in computational molecular biology
Evaluation of Placement Techniques for DNA Probe Array Layout
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improving the layout of oligonucleotide microarrays: pivot partitioning
WABI'06 Proceedings of the 6th international conference on Algorithms in Bioinformatics
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.00 |
Optimal design of DNA arrays for very large-scale immobilized polymer synthesis (VLSIPS) [3] seeks to minimize effects of unintended illumination during mask exposure steps. Hannenhalli et al. [6] formulate this requirement as the Border Minimization Problem and give an algorithm for placement of probes at array sites under the assumption that the array synthesis is synchronous, i.e., nucleotides are synthesized in a periodic sequence (ACGT)k and every probe grows by exactly one nucleotide with every group of four masks. Their method reduces the number of conflicts, i.e., total mask border length, by 20-30% versus the previous standard method for array design. In this paper, we propose a probe placement algorithm for synchronous array synthesis which reduces the number of conflicts by up to 10% versus the method of Hannenhalli et al [6]. We also consider the case of asynchronous array synthesis, and present new heuristics that reduce the number of conflicts by up to a further 15.5-21.8%. Finally, we give lower bounds that offer insights into the amount of available further improvements. The paper concludes with several directions for future research.