A module interchange placement machine
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic placement algorithms for high packing density V L S I
DAC '83 Proceedings of the 20th Design Automation Conference
A placement algorithm for array processors
DAC '83 Proceedings of the 20th Design Automation Conference
A systolic design rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Hardware accelerators in the design automation environment
DAC '84 Proceedings of the 21st Design Automation Conference
GALA - an automatic layout system for high density CMOS gate arrays
DAC '84 Proceedings of the 21st Design Automation Conference
The cytocomputer: A practical pipelined image processor
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
Hardware support for automatic routing
DAC '82 Proceedings of the 19th Design Automation Conference
Global wiring on a wire routing machine
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
A bit map architecture and algorithms for design automation
A bit map architecture and algorithms for design automation
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Multiprocessor-based placement by simulated annealing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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In this paper we describe the hardware and software of a system which we have implemented to accelerate the physical design of gate arrays. In contrast to nearly all other reported approaches, our approach to hardware acceleration is to augment a single-user host workstation with a general-purpose microprogrammable slave processor having a large private memory. One or more such slaves can be attached. We have implemented placement improvement on the system, achieving a 20 x speedup vs. a high-level host implementation. We give performance results, which are comparable to those reported elsewhere for mainframe implementations.