Hardware acceleration of gate array layout
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A module interchange placement machine
DAC '83 Proceedings of the 20th Design Automation Conference
A placement algorithm for array processors
DAC '83 Proceedings of the 20th Design Automation Conference
Parallel algorithms for chip placement by simulated annealing
IBM Journal of Research and Development
Performance of a parallel algorithm for standard cell placement on the Intel hypercube
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Enhanced simulated annealing for automatic reconfiguration of multiprocessors in space
IEA/AIE '89 Proceedings of the 2nd international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 1
Heuristic Technique for Processor and Link Assignment in Multicomputers
IEEE Transactions on Computers
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
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Simulated annealing methods have proven to be particularly successful in physical design applications, but often require burdensome, long run times. This paper studies the design and analysis of standard cell placement by annealing in a multiprocessor environment. Annealing is not static: we observe that the temperature parameter which controls hill-climbing in simulated annealing changes the behavior of an annealing algorithm as it runs, and strongly influences the choice of multiprocessor partitioning strategy. We introduce the idea of adaptive strategies that exhibit different speedups across different temperature ranges. Measured performance of parallel placement algorithms running on a multiprocessor demonstrate practical speedups consistent with our predictions.