Communications of the ACM - Special section on computer architecture
Parallel implementations of the statistical cooling algorithm
Integration, the VLSI Journal
Multigrid Algorithms on the Hypercube Multiprocessor
IEEE Transactions on Computers
Performance of a parallel algorithm for standard cell placement on the Intel hypercube
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Almost all k-colorable graphs are easy to color
Journal of Algorithms
iPSC/2 system: a second generation hypercube
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
A parallel row-based algorithm for standard cell placement with integrated error control
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Multiprocessor-based placement by simulated annealing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
New methods to color the vertices of a graph
Communications of the ACM
Parallel Simulated Annealing: Accuracy vs. Speed in Placement
IEEE Design & Test
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
On a parallel partitioning technique for use with conservative parallel simulation
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Relaxing Synchronization in Distributed Simulated Annealing
IEEE Transactions on Parallel and Distributed Systems
ICS '96 Proceedings of the 10th international conference on Supercomputing
Synchronous and Asynchronous Parallel Simulated Annealing with Multiple Markov Chains
IEEE Transactions on Parallel and Distributed Systems
Chromosome Reconstruction from Physical Maps Using a Cluster of Workstations
The Journal of Supercomputing
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Mesh Partitioning for Efficient Use of Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Evolutionary Approaches to Figure-Ground Separation
Applied Intelligence
Parallel N-ary Speculative Computation of Simulated Annealing
IEEE Transactions on Parallel and Distributed Systems
An Inherently Parallel Method for Heuristic Problem-Solving: Part I-General Framework
IEEE Transactions on Parallel and Distributed Systems
Using PVM for Distributed Logic Minimization in a Network of Computers
Proceedings of the 6th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Parallel simulated annealing strategies for VLSI cell placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Parallel adaptive simulated annealing for computer-aided measurement in functional MRI analysis
Expert Systems with Applications: An International Journal
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Multilevel Task Partition Algorithm for Parallel Simulation of Power System Dynamics
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part I: ICCS 2007
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Simulated annealing techniques
Algorithms and theory of computation handbook
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A discussion is presented of two ways of mapping the cells in a two-dimensional area of a chip onto processors in an n-dimensional hypercube such that both small and large cell moves can be applied. Two types of move are allowed: cell exchanges and cell displacements. The computation of the cost function in parallel among all the processors in the hypercube is described, along with a distributed data structure that needs to be stored in the hypercube to support such a parallel cost evaluation. A novel tree broadcasting strategy is presented for the hypercube that is used extensively in the algorithm for updating cell locations in the parallel environment. A dynamic parallel annealing schedule is proposed that estimates the errors due to interacting parallel moves and adapts the rate of synchronization automatically. Two novel approaches in controlling error in parallel algorithms are described: heuristic cell coloring and adaptive sequence control. The performance on an Intel iPSC-2/D4/MX hypercube is reported.