Performance of a parallel algorithm for standard cell placement on the Intel hypercube

Authors:
M. Jones;P. Banerjee
Affiliations:
Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign;Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

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Abstract

In this paper, we present a parallel simulated annealing algorithm for standard cell placement that is targeted to run on the Intel Hypercube. We present a novel tree broadcasting strategy that is used extensively in our algorithm for updating cell locations in the parallel environment. Studies on the performance of our algorithm on example industrial circuits show that it is faster and gives better final placement results than the uniprocessor simulated annealing algorithms.