Performance of a parallel algorithm for standard cell placement on the Intel hypercube
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A parallel row-based algorithm for standard cell placement with integrated error control
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic layout of analog and digital mixed macro/standard cell integrated circuits
Automatic layout of analog and digital mixed macro/standard cell integrated circuits
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Accurate net models for placement improvement by network flow methods
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement
Proceedings of the 8th International Symposium on Parallel Processing
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Parallel simulated annealing strategies for VLSI cell placement
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Speeding up FPGA placement via partitioning and multithreading
International Journal of Reconfigurable Computing
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of our algorithm is targeted towards networks of UNIX workstations. This is the very first reported parallel algorithm for standard cell placement which yields as good or better placement results than its serial version. In addition, it is the first parallel placement algorithm reported which offers nearly linear speedup, in terms of the number of processors (workstations) used, over the serial version. Despite using the rather slow local area network as the only means of interprocessor communication, the processor utilization is quite high, up to 98% for 2 processors and 90% for 6 processors. The new parallel algorithm has yielded the best overall results ever reported for the set of MCNC standard cell benchmark circuits.