A hardware accelerator for maze routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Hardware Accelerator for Maze Routing
IEEE Transactions on Computers
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Hardware acceleration of gate array layout
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Multiprocessor-based placement by simulated annealing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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In this report a concurrent pairwise exchange placement algorithm executing on an array processor is presented. Two force functions and their effects are discussed. The oscillation phenomenon caused by the concurrent computation is investigated and some solutions are suggested. A design for the array processor is presented along with a complexity analysis which indicates that this algorithm is O(N2) faster than a conventional sequential placement algorithm if N×N processors are employed.