Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Optimal wiring between rectangles
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
The complexity of design automation problems
DAC '80 Proceedings of the 17th Design Automation Conference
An optimal solution to a wire-routing problem (preliminary version)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
The minimum width routing of A 2-row 2-layer polycell-layout
DAC '79 Proceedings of the 16th Design Automation Conference
ALGORITHMS FOR INTEGRATED CIRCUIT LAYOUT: AN ANALYTIC APPROACH
ALGORITHMS FOR INTEGRATED CIRCUIT LAYOUT: AN ANALYTIC APPROACH
Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Routing L-shaped channels in nonslicing-structure placement
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Routing with a scanning window-8Ma unified approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Maximum Alignment of Interchangeable Terminals
IEEE Transactions on Computers
An expert system for channel routing
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 2
25 years of DAC Papers on Twenty-five years of electronic design automation
VIA minimization by layout modification
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
MISER: an integrated three layer gridless channel router and compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A multi-layer router utilizing over-cell areas
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
General models and algorithms for over-the-cell routing in standard cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Using controlled experiments in layout
ACM SIGDA Newsletter
Novel routing schemes for IC layout part I: Two-layer channel routing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Channel density reduction by routing over the cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A general multi-layer area router
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routing through a dense channel with minimum total wire length
SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
A pin permutation algorithm for improving over-the-cell channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Over-the-cell channel routing for high performance circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Over-the-cell routers for new cell model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An optimal channel pin assignment with multiple intervals for building block layout
EURO-DAC '92 Proceedings of the conference on European design automation
Channel routing of multiterminal nets
Journal of the ACM (JACM)
Improving over-the-cell channel routing in standard cell design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Nearly optimal algorithms and bounds for multilayer channel routing
Journal of the ACM (JACM)
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
How to obtain more compactable channel routing solutions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Minimizing channel density by lateral shifting of components
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
An algorithm for one and half layer channel routing
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
WEAVER: a knowledge-based routing expert
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Hardware acceleration of gate array layout
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An industrial world channel router for non-rectangular channels
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Chameleon: a new multi-layer channel router
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A new approach to multi-layer PCB routing with short vias
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Near-optimal n-layer channel routing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Manhattan channel routing with good theoretical and practical performance
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
Recent results in VLSI CAD at MIT
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Three-layer bubble-sorting-based nonManhattan channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An exact algorithm for solving difficult detailed routing problems
Proceedings of the 2001 international symposium on Physical design
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
A wire routing scheme for double-layer cell arrays
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A switchbox router with obstacle avoidance
DAC '84 Proceedings of the 21st Design Automation Conference
An approximation algorithm for manhattan routing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
Channel routing in Manhattan-diagonal model
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Optimal via-shifting in channel compaction
EURO-DAC '90 Proceedings of the conference on European design automation
Channel routing with non-terminal doglegs
EURO-DAC '90 Proceedings of the conference on European design automation
Manhattan-diagonal routing in channels and switchboxes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A genetic algorithm for channel routing in vlsi circuits
Evolutionary Computation
The star-routing algorithm based on Manhattan-Diagonal model for three layers channel routing
WSEAS Transactions on Circuits and Systems
Algorithms for permutation channel routing
Integration, the VLSI Journal
Paper: An application of neural networks on channel routing problem
Parallel Computing
Algorithms and theory of computation handbook
Multilevel routing for 3-dimensional circuits
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
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We present a new, “greedy”, channel-router that is quick, simple, and highly effective. It always succeeds, usually using no more than one track more than required by channel density. (It may be forced in rare cases to make a few connections “off the end” of the channel, in order to succeed.) It assumes that all pins and wiring lie on a common grid, and that vertical wires are on one layer, horizontal on another. The greedy router wires up the channel in a left-to-right, column-by-column manner, wiring each column completely before starting the next. Within each column the router tries to maximize the utility of the wiring produced, using simple, “greedy” heuristics. It may place a net on more than one track for a few columns, and “collapse” the net to a single track later on, using a vertical jog. It may also use a jog to move a net to a track closer to its pin in some future column. The router may occasionally add a new track to the channel, to avoid “getting stuck”.