Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Patchwork: layout from schematic annotations
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An industrial world channel router for non-rectangular channels
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
A gridless multi-layer router for standard cell circuits using CTM cells
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Many automatic layout systems for VLSI circuits employ channel routing as the basic interconnection function. The wide range of uses and the importance of channel routing have inspired many good channel routing algorithms. However, many algorithms were developed with the geometric regularity of standard cell and gate array designs in mind. As a result these algorithms have difficulty routing channels with geometric generality (rectilinear boundaries and wires and terminals that can have different widths and irregular spacings) and simultaneously guaranteeing completion of all routes. This paper presents an algorithm for resolving cyclic vertical constraints using a general channel model. When this algorithm is combined with a constraint-based channel router, routing completion can be guaranteed, even for routing problems with generalized geometries. This algorithm is implemented with a constrain-based, alternating-edge, dogleg channel router. Extensions are described which permit the channel router to implement switchbox routing.