Layout design and verification
Layout design and verification
Routing L-shaped channels in nonslicing-structure placement
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Information Processing Letters
A 2d channel router for the diagonal model
Integration, the VLSI Journal
Novel routing schemes for IC layout part I: Two-layer channel routing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Nearly optimal algorithms and bounds for multilayer channel routing
Journal of the ACM (JACM)
Three-layer bubble-sorting-based nonManhattan channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Artificial Intelligence Approach to VLSI Routing
Artificial Intelligence Approach to VLSI Routing
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Computing area and wire length efficient routes for channels
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Partitioning VLSI Floorplans by Staircase Channels for Global Routing
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
A density-based general greedy channel routing algorithm in vlsi design automation
A density-based general greedy channel routing algorithm in vlsi design automation
Minimizing the number of switchboxes for region definition and ordering assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Asynchronous distributed genetic algorithm for optimal channel routing
CIS'04 Proceedings of the First international conference on Computational and Information Science
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New techniques are presented for routing straight channels, L-channels, switchboxes, and staircase channels in a two-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical, and ± 45° directions. First, an O(l.d) time algorithm is presented for routing a straight channel of length l and density d with no cyclic vertical constraints. It is shown that the number of tracks h used by the algorithm for routing multiterminal nets satisfies d ≤ h ≤ (d + 1). Second, an output-sensitive algorithm is reported that can route a channel with cyclic vertical constraints in O(l.h) time using h tracks, allowing overlapping of wire segments in two layers. Next, the routing problem for a multiterminal L-channel of length l and height h is solved by an O(l.h) time algorithm. If no cyclic vertical constraints exist, its time complexity reduces to O(l.d) where d is the density of the L-channel. Finally, the switchbox routing problem in the MD model is solved elegantly. These techniques, easily extendible to the routing of staircase channels, yield efficient solutions to detailed routing in general floorplans. Experimental results on benchmarks show significantly low via count and reduced wire length, thus establishing the superiority of MD routing to classical strategies. The proposed algorithms are also potentially useful for general non-Manhattan area routing and multichip modules (MCMs).