Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
A faster deterministic maximum flow algorithm
SODA selected papers from the third annual ACM-SIAM symposium on Discrete algorithms
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Monotone bipartitioning problem in a planar point set with applications to VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
On finding an empty staircase polygon of largest area (width) in a planar point-set
Computational Geometry: Theory and Applications
Manhattan-diagonal routing in channels and switchboxes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven repeater block planning for interconnect-centric floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel global placement with congestion control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This article addresses the problem of recursively bipartitioning a given floorplan F using monotone staircases. At each level of the hierarchy, a monotone staircase from one corner of F to its opposite corner is identified, such that (i) the two parts of the bipartition are nearly equal in area (or in the number of blocks), and (ii) the number of nets crossing the staircase is minimal. The problem of area-balanced bipartitioning is shown to be NP-hard, and a maxflow-based heuristic is proposed. Such a hierarchy may be useful to repeater placement in deep-submicron physical design, and also to global routing.