Generation of very large circuits to benchmark the partitioning of FPGA
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
Min-cut program decomposition for thread-level speculation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph partitioning through a multi-objective evolutionary algorithm: a preliminary study
Proceedings of the 10th annual conference on Genetic and evolutionary computation
A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
| Hi-index | 0.03 |
We consider the problem of bipartitioning a circuit into two balanced components that minimizes the number of crossing nets. Previously, Kernighan and Lin type (K&L) heuristics, simulated annealing approach, and analytical methods were given to solve the problem. However, network flow (max-flow min-cut) techniques were overlooked as viable heuristics to min-cut balanced bipartition due to their high complexity. In this paper we propose a balanced bipartition heuristic based on repeated max-flow min-cut techniques, and give an efficient implementation that has the same asymptotic time complexity as that of one max-flow computation. We implemented our heuristic algorithm in a package called FBB. The experimental results demonstrate that FBB outperforms K&L heuristics and analytical methods in terms of the number of crossing nets, and our efficient implementation makes it possible to partition large circuit netlists with reasonable runtime. For example, the average elapsed time for bipartitioning a circuit S35932 of almost 20 K gates is less than 20 min on a SPARC10 with 32 MB memory