Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Monotone bipartitioning problem in a planar point set with applications to VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to Algorithms, Third Edition
Introduction to Algorithms, Third Edition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This work proposes an improved heuristic algorithm for top-down hierarchical Monotone Staircase Bipartitioning of VLSI floorplans using breadth-first traversal to reduce the runtime to O(nk) at each level of the hierarchy, where n and k denote respectively the number of blocks and nets in the given floorplan. This multi-objective optimization problem calls for a trade off between maximizing the quality of area (number) balanced bipartition, and minimizing the number of cut nets at each level of the hierarchy by a trade-off parameter γ∈[0,1]. The area balanced bipartition is known to be a NP-hard problem. The proposed approach obtains a bipartition as close to balanced (ideally equal area or number as the case may be) as possible along with a minimal net cut. We obtain convex weighted linear cost as high as 0.998 for γ = 0.4, and the runtime does not exceed 1 second for any of the circuits in MCNC/GSRC Hard floorplanning benchmarks. This method, without using maxflow algorithm, is much faster and simpler than the earlier maxflow-based approach, without sacrificing the quality of the solution.