Discrete-time signal processing
Discrete-time signal processing
Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Network flow based circuit partitioning for time-multiplexed FPGAs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network-flow-based multiway partitioning with area and pin constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generic ILP-based approaches for time-multiplexed FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temporal logic replication for dynamically reconfigurable FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combining temporal partitioning and temporal placement techniques for communication cost improvement
Advances in Engineering Software
Hierarchical loop partitioning for rapid generation of runtime configurations
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Functionally verifying state saving and restoration in dynamically reconfigurable systems
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
A goal-oriented programming framework for grid sensor networks with reconfigurable embedded nodes
ACM Transactions on Embedded Computing Systems (TECS)
Temporal partitioning of data flow graphs for reconfigurable architectures
International Journal of Computational Science and Engineering
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FPGA-based configurable computing machines are evolving rapidly in large signal processing applications due to flexibility and high performance. In this paper, given a reconfigurable processing unit (RPU) with a logic capacity of ARPU and a computational task represented by a data flow graph G = (V, E, W), we propose a network flow-based multiway task partitioning algorithm to minimize communication costs for temporal partitioning. The proposed algorithm obtains an optimal solution with minimum interconnection under area constraints. The optimal solution is a cut set. In our approach, two techniques are applied. In the initial partition, any feasible min-cut is produced by the proposed network flow-based algorithm, so a set of feasible min-cuts is obtained. From the feasible solutions, the scheduling technique selects an optimal global solution.