MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
Proceedings of the 37th Annual Design Automation Conference
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Parallel Processing Architectures for Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Memory System Design Space Exploration for Low-Power, Real-Time Speech Recognition
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Computer Organization and Architecture: Designing for Performance (7th Edition)
Computer Organization and Architecture: Designing for Performance (7th Edition)
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
The wild west: conquest of complex hardware-dependent software design
Proceedings of the 46th Annual Design Automation Conference
Generic ILP-based approaches for time-multiplexed FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the Scalable Video Coding Extension of the H.264/AVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
Graph based M2M optimization in an IoT environment
Proceedings of the 2013 Research in Adaptive and Convergent Systems
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Computational load of motion estimation in advanced video coding (AVC) standard is significantly high and even worse for HDTV and super-resolution sequences. In this article, a video processing algorithm is dynamically mapped onto a new parallel reconfigurable computing (PRC) architecture which consists of multiple dynamic reconfigurable computing (DRC) units. First, we construct a directed acyclic graph (DAG) to represent video coding algorithms in which motion estimation is the focus. A novel parallel partition approach is then proposed to map motion estimation DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different search ranges. This speeds up the video processing with minimum sacrifice.