Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
An Effective Design System for Dynamically Reconfigurable Architectures
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast place and route approaches for fpgas
Fast place and route approaches for fpgas
Temporal logic replication for dynamically reconfigurable FPGA partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient datapath merging for the overhead reduction of run-time reconfigurable systems
The Journal of Supercomputing
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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In reconfigurable systems, reconfiguration latency is a very important factor impact the system performance. In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. A temporal partitioning algorithm is proposed which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. This algorithm attempts to find similar single or pair of operations between subsequent partitions. Considering similar pairs instead of single nodes brings about less complexity for routing process. By using this technique, smaller reconfiguration bit-stream is obtained, which directly decreases the reconfiguration overhead time at the run-time. A complementary algorithm attempts to increase the similarity of subsequent partitions by searching for similar pairs and using a technique called dummy node insertion. An incremental physical design process based on similar configurations produced in the partitioning stage improves the metrics over iterations.