Temporal partitioning data flow graphs for dynamically reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A minimum communication cost algorithm for dynamically reconfigurable computing system
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power minimization for dynamically reconfigurable FPGA partitioning
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. We show that this is a very effective means to reduce the communication cost by taking advantage of the slack logic capacity available. Given a K-stage temporal partition, the min-area min-cut replication problem is defined and we present an optimal algorithm to solve it. We also present a flow-based replication heuristic which is applicable when there is a tight area bound that limits the amount of possible replication. In addition, we show a correct network flow model for partitioning sequential circuits temporally and propose a new hierarchical flow-based performance-driven partitioner for computing initial partitions without replication.