Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A C to HDL Compiler for Pipeline Processing on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Designing cad tools for reconfigurable computing
Designing cad tools for reconfigurable computing
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Proceedings of the 42nd annual Design Automation Conference
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Automated design of digital microfluidic lab-on-chip under pin-count constraints
Proceedings of the 2008 international symposium on Physical design
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ever-growing performance expectations of such systems, designers need new methodologies and tools for developing reconfigurable computing systems (RCS). This paper addresses the need for fast compilation and physical design phase to be used in application development / debugging / testing cycle for RCS. We present a high-level synthesis approach that is integrated with placement, making the compilation cycle much faster. On the average, our tool generates the VHDL code (and the corresponding placement information) from the data flow graph of a program in less than a minute. By compromising 30% in the clock frequency of the circuit, we can achieve about 10 times speedup in the Xilinx placement phase, and 2.5 times overall speedup in the Xilinx place-and-route phase, a reasonable trade-off when developing RCS applications.