Optimizing FPGA-Based Vector Product Designs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Proceedings of the 38th annual Design Automation Conference
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
A Reconfigurable Processor Infrastructure for Accelerating Java Applications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Jaguar: a compiler infrastructure for java reconfigurable computing
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
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In this paper, we show a compiler that generates high-speed pipeline circuits for loop and recursive programs written in C programming language, which are the most time exhaustive parts in many application problems. The compiler has following features. First, all operations (except for memory accesses) are divided into cascades of 8-bit width (at maximum) operations in order to achieve high-speed clock cycle. Second, in order to full fill the pipeline, variables that have data feedback dependencies between loops cycles are specially scheduled based on several kinds of optimizing techniques.Furthermore, computations of each loop cycle are speculatively started in every clock cycle even if an array on the same memory bank may be accessed more than once in a loop cycle and there may be data feedback dependencies caused by the array accesses. When the array is accessed more than once, the pipeline is stalled while the array access operations are executed sequentially, and when the feedback dependencies are detected, the speculative computations are cancelled, and restarted after the updates of array are finished. Experiments on simple combinatorial programs showed that the pipeline circuits generated by the compiler run about 39-47MHz on ALTERA EPF10KA serious (which is as fast as hand optimized circuits), and the speed up by the speculative execution is more than two.