Evaluation of the streams-C C-to-FPGA compiler: an applications perspective

  • Authors:

  • Jan Frigo;Maya Gokhale;Dominique Lavenier

  • Affiliations:

  • Los Alamos National Laboratory, Los Alamos, NM;Los Alamos National Laboratory, Los Alamos, NM;IRISA - CNRS, Campus de Beaulieu, 35042 Rennes cedex, France

  • Venue:
  • FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
  • Year:
  • 2001

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Abstract

The Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. The Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. The processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated.The Streams-C language and compiler offer a very high level of expressivity for reconfigurable computing application development, particularly for stream-processing applications. We find this is reflected in productivity, for a factor of up to 10 times improvement in time to produce a program. However, use of the tool in the ``real world'' is predicated on performance: only if such a compiler can deliver performance comparable to hand-coded performance will it be used in practice.This paper presents an application study of the Streams-C compiler. Four applications have been written in Streams-C and compiled to the AMC Wildforce board containing Xilinx 4036's. Those same applications have been hand-coded in a combination of RTL and structural VHDL. We compare performance of the generated code with the hand-optimized code. Our study shows that the compiler-generated designs are 1.37--4 times the area and $1/2$--1 times the clock frequency of the hand designs. We find that the compiler, based on the SUIF infrastructure, can be greatly improved through various standard compiler optimizations that are not currently being exploited. Thus we are currently re-writing a public domain version of Streams-C to better optimize and target the Virtex chip.