Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Modern Logic Design
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
High level compilation for fine grained FPGAs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Pipeline Vectorization for Reconfigurable Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Performance-constrained pipelining of software loops onto reconfigurable hardware
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Experience with a Hybrid Processor: K-Means Clustering
The Journal of Supercomputing
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Code transformations for embedded reconfigurable computing architectures
GTTSE'09 Proceedings of the 3rd international summer school conference on Generative and transformational techniques in software engineering III
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Hybrid architectures combining conventional processors withconfigurable logic resources enable efficient coordination of controlwith datapath computation. With integration of the two components ona single device, housekeeping tasks and, optionally, loop control anddata-dependent branching, can be handled by the conventionalprocessor, while regular datapath computation occurs on theconfigurable hardware. This paper describes a novel approach toprogramming such hybrid devices that gives the programmer controlover mapping of data and computation between conventional processorand configurable logic. With a simple set of pragma and intrinsicfunction directives, the NAPA C language provides for manual controlover perhaps the most important aspect of programming such hybriddevices. Alternatively, as experience is gained about tradeoffsbetween the two computational resources, mapping directives mayeventually be generated by an external tool. The paper furtherdescribes a research prototype compiler that targets the hybridprocessor model, with a concrete implementation for the NationalSemiconductor NAPA1000 chip. The NAPA C compiler parses the mappingdirectives, performs semantic analysis, and co-synthesizes aconventional processor executable combined with a configuration bitstream for the configurable logic. Two major compiler phases, thesynthesis of pipelined loops and the datapath synthesis, aredescribed in detail.