Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Understanding retiming through maximum average-weight cycles
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Efficient and exact data dependence analysis
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Scheduling and resource binding for low power
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Exploiting instruction level parallelism in the presence of conditional branches
Exploiting instruction level parallelism in the presence of conditional branches
Circuit Retiming Applied to Decomposed Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
A practical approach to multiple-class retiming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Co-Synthesis to a Hybrid RISC/FPGA Architecture
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Adapting software pipelining for reconfigurable computing
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
An efficient search algorithm to find the elementary circuits of a graph
Communications of the ACM
Power-aware modulo scheduling for high-performance VLIW processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining"
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Optimal Retiming for Initial State Computation
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cycle-time aware architecture synthesis of custom hardware accelerators
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
Combining module selection and resource sharing for efficient FPGA pipeline synthesis
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
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Retiming and slowdown are algorithms that can be used to pipeline synchronous circuits. Iterative modulo scheduling is an algorithm for software pipelining in the presence of resource constraints. Integrating the best features of both yields a pipelining algorithm, retimed modulo scheduling, that can more effectively exploit the idiosyncrasies of reconfigurable hardware. It also fits naturally into a design space exploration process to trade-off speed for power, energy or area.