Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding
IEEE Transactions on Computers
Sequential circuit delay optimization using global path delays
DAC '93 Proceedings of the 30th international Design Automation Conference
Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The chaos router chip: design and implementation of an adaptive router
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Combining MBP-speculative computation and loop pipelining in high-level synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control
DAC '97 Proceedings of the 34th annual Design Automation Conference
Using precomputation in architecture and logic resynthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Retiming-based factorization for sequential logic optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On speeding up extended finite state machines using catalyst circuitry
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
Performance-constrained pipelining of software loops onto reconfigurable hardware
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Optimization of synchronous circuits
Logic Synthesis and Verification
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register Transformations with Multiple Clock Domains
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing sequential cycles through Shannon decomposition and retiming
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Integration, the VLSI Journal
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
Automatic microarchitectural pipelining
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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