Performance optimization of digital circuits
Performance optimization of digital circuits
Performance optimization using exact sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Architectural retiming: pipelining latency-constrained circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Performance-driven integration of retiming and resynthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level automatic pipelining for sequential circuits
Proceedings of the 14th international symposium on Systems synthesis
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
On decomposing Boolean functions via extended cofactoring
Proceedings of the Conference on Design, Automation and Test in Europe
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Synthesis of P-circuits for logic restructuring
Integration, the VLSI Journal
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Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pipelines, but it is stymied by tight sequential cycles. Designers usually attack such cycles by manually combining Shannon decomposition with retiming---effectively a form of speculation---but such manual decomposition is error-prone.We propose an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles. While the algorithm is only able to improve certain circuits (roughly half of the benchmarks we tried), the performance increase can be dramatic (7%--61%) with only a modest increase in area (3%--12%). The algorithm is also fast, making it a practical addition to a synthesis flow.