Temperature-insensitive synthesis using multi-vt libraries

Authors:
Andrea Calimera;Enrico Macii;Massimo Poncino;R. Iris Bahar
Affiliations:
Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy;Brown University, Providence, RI, USA
Venue:
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Year:
2008

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Abstract

Temperature fluctuations can alter the delay in MOS circuits. However, increases in temperature do not always lead to a corresponding increase in circuit delay, specifically when operating at low supply voltages. Instead a temperature inversion effect can be observed on the delay of MOS devices under certain conditions, where the delay actually decreases as temperature increases. Given these non-monotonic effects, guaranteeing timing correctness can no longer be achieved simply by characterizing the design under worst case (i.e., high temperature) conditions. In this paper, we present a synthesis methodology in which multi-Vth design is used to generate temperature-insensitive circuits, while minimizing leakage power dissipation as a side-effect. Our experiments with ISCAS benchmark circuits demonstrate the promise of this approach and show that significant reduction in static power is also possible.