Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Authors:
Andrea Calimera;R. Iris Bahar;Enrico Macii;Massimo Poncino
Affiliations:
Politecnico di Torino, Torino, Italy;Brown University, Providence, RI, USA;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy
Venue:
Proceedings of the 13th international symposium on Low power electronics and design
Year:
2008

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Abstract

The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in Vth can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-Vt design; in particular, we show how traditional dual-Vt optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.