Fitting polygonal functions to a set of points in the plane
CVGIP: Graphical Models and Image Processing
Efficient piecewise-linear function approximation using the uniform metric: (preliminary version)
SCG '94 Proceedings of the tenth annual symposium on Computational geometry
Temperature effect on delay for low voltage applications
Proceedings of the conference on Design, automation and test in Europe
Detection of Temperature Sensitive Defects Using ZTC
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Temperature-insensitive synthesis using multi-vt libraries
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 13th international symposium on Low power electronics and design
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Inversed temperature dependence aware clock skew scheduling for sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Body bias voltage computations for process and temperature compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference on Computer-Aided Design
Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Integration, the VLSI Journal
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In digital circuit design, it is typically assumed that cell delay increases with decreasing voltage and increasing temperature. This assumption is the basis of the cornering approach with cell libraries in static timing analysis (STA). However, this assumption breaks down at low supply voltages because cell delay can decrease with increasing temperature. This phenomenon is caused by a competition between mobility and threshold voltage to dominate cell delay. We refer to this phenomenon as the inverted temperature dependence (ITD). Due to ITD, it becomes very difficult to analytically determine the temperatures that maximize or minimize the delay of a cell or a path. As such, ITD has profound consequences for STA: (1) ITD essentially invalidates the approach of defining corners by independently varying voltage and temperature; (2) ITD makes it more difficult to find short paths, leading to difficulties in detecting hold time violations; and (3) the effect of ITD will worsen as supply voltages decrease and threshold voltage variations increase. This article analyzes the consequences of ITD in STA and proposes a proper handling of ITD in an industrial sign-off STA tool. To the best of our knowledge, this article is the first such work.