Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Handling inverted temperature dependence in static timing analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Proceedings of the 50th Annual Design Automation Conference
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In 3D ICs, TSV-induced thermal residual stress impacts transistor mobilities due to the piezoresistive effect. This phenomenon is coupled with other temperature effects on transistor parameters that are seen even in the absence of TSVs. In this paper, analytical models are developed to holistically represent the effect of thermally-induced variations on circuit timing. The analysis is based on a semianalytic formulation that is demonstrated to accurately capture the biaxial nature of TSV stress and its effect on delay.