A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 48th Design Automation Conference
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Proceedings of the 49th Annual Design Automation Conference
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
Proceedings of the 49th Annual Design Automation Conference
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Thermal stress aware 3D-IC statistical static timing analysis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Proceedings of the 50th Annual Design Automation Conference
A study of tapered 3-D TSVs for power and thermal integrity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we propose an efficient and accurate full-chip thermo-mechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the use of the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs. Our experimental results demonstrate the effectiveness of our methodology.